1. Field of the Invention
The present invention relates to a method and apparatus for recording and reproducing information, and more particularly, to a method and apparatus for recording and reproducing information capable of achieving high-speed error correction.
2. Description of the Related Art
Generally, in recording data in a memory card, efficient data manipulation is enabled by allocation of a physical recording area to logical space. Physical-to-logical mapping is performed by a method in which, as shown in FIG. 6, a logical address is assigned to each of physical constituent units (A, B, C, . . . ). When the memory card is used, all logical addresses therein are read first, followed by creation of a logical/physical address translation table which is used for translation from logical to physical addresses thereby to allocate the recording area to the logical space, so that non-contiguously recorded data set is made contiguous in a virtual space.
During production or use of the memory card, part of its storage elements is occasionally damaged, leading to an erroneous logical address read from the card.
In order to detect and correct such erroneous data or logical address, error correction coding technique has been employed in which, as shown in FIG. 7, individual constituent units in the physical space include extra redundant data which is an error correcting code, such as Reed Solomon code, calculated for a set of data, added information and logical address, so as thereby to correct the error using this error correcting code.
Also, disclosed in the Japanese Patent Application Publication No. 6-52697 is error correcting technique for semiconductor memory, wherein an odd number of three or more memory cells have the same one bit of the same one address so that error correction is made by determination based on majority voting in readout time.
Such an error correction coding technique as Reed Solomon coding, however, disadvantageously requires much time for decoding contrary to the necessity of promptly reading logical addresses and speedily creating the logical/physical address translation table.